Increased performance in circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor (e.g., silicon) substrate) is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons in N-type MOS device (NMOS) channels and to increase movement of positive charged holes in P-type MOS device (PMOS) channels. To increase movement of electrons and holes, (e.g., also referred to as “charge carriers”), feature sizes of the transistor devices are often reduced. For example, the channel length of a device may be shortened so that charge carriers move from one junction region to another more quickly. Reduction in channel length may lead to excessive leakage current if the doped junction (or source/drain) regions of the transistor become too close together. This can happen if the junction region dopants diffuse beyond the desired doping region due to subsequent thermal treatment. For example, for a PMOS device, boron out-diffusion may extend from the junction regions into the channel, thus increasing leakage current between the junction regions. Similarly, when gate length is reduced, short channel effects may suffer unless the lateral depletion region is reduced as well. Thus, during design and manufacture of PMOS devices, it is often desired to reduce boron out-diffusion from P-type junction regions into the channel during thermal treatment of the device after forming the junction regions. Similarly, during such design, it is often desired to reduce leakage current amounts and the lateral depletion width between junction regions and the channel.